SystemVerilog for Design
This 3 day course is aimed at RTL Designers who wish to learn about the design features of SystemVerilog. It starts with a review of Verilog design features and also includes SystemVerilog Assertions.

SystemVerilog for Verification
This 4 day course is aimed at experienced Verification engineers who wish to learn about verification with SystemVerilog.

Also available On Demand 

SystemVerilog Assertions (SVA)
This one day course is targeted at Design and Verification engineers who wish to deploy Assertion based Verification within their next project.

Also available On Demand 

Object Oriented Programming with SystemVerilog
For Verification engineers who want to move beyond the basics, this two day course covers all the types of classes in SystemVerilog and describes a dozen of the most useful design patterns. Discusses the why of each pattern, not just the how.

Introduction to Universal Verification Methodology (UVM)
This 4 day course is for engineers interested in developing SystemVerilog verification environments using the latest Universal Verification Methodology (UVM).

Also available On Demand 

Advanced Universal Verification Methodology (UVM)
This three-day workshop is designed for UVM users who want to take their skills to the next level.

Introduction to Verilog for RTL Design
A 3 day course teaching designers to write efficient, accurate RTL code for synthesis as well as basic testbenching and verification techniques.