Advanced Universal Verification Methodology (UVM)
This three-day workshop is designed for UVM users who want to take their skills to the next level.
Putting together real world testbenches require more than just knowing the components of the UVM library. Real world testbenches have issues that require knowing how to apply the UVM library to solve them. Issues such as multiple interfaces to the DUT, layering stimulus, concurrent process synchronization, dealing with behaviors such as interrupts and multiple response types, and building scalable, reusable testbenches are addressed.
In this Advanced UVM class you will gain experience in dealing with these and other testbench challenges. The class works through various testbench issues and challenges providing solutions. You will be able to apply these solutions to your testbench. You will also take away from this class detailed real world example testbenches that provide a great reference in doing your testbench.
- DUT-TB Interface
- Container Classes
- Process synchronization
- Advanced Phasing
- Virtual sequences
- Response handling
- Interrupt handling
- Layered stimulus
- UVM Register Model integration
- UVM Register Memory Allocation Manager
- Template Method Pattern and UVM Callbacks
- Command Line processing
- Emulation considerations
- Coverage driven testing
A good portion of class time will be spent applying principles learned in lecture to hands-on labs.
This is an advanced class and students are expected to have actual UVM experience or have taken our UVM Introductory course plus experience.