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WHDL courses continue to be available via Hardent .

Hardent offers a wide variety of training and consulting in the areas of FPGA and ASIC Design and Verification. The most popular courses are available in self-learning on-demand form as well, follow the links below.

Don't forget that all courses can be customized to best match the needs of your team

SystemVerilog Courses

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SystemVerilog for Design
This 2 day course is aimed at RTL Designers who wish to learn about the design features of SystemVerilog. An optional 1 day precursor course is available for designers new to Verilog RTL.

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SystemVerilog for Verification
This 4 day course is aimed at experienced Verification engineers who wish to learn about verification with SystemVerilog.

Also available On Demand 

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SystemVerilog Assertions (SVA)
This one day course is targeted at Design and Verification engineers who wish to deploy Assertion based Verification within their next project.

Also available On Demand 

UVM Courses

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Introduction to Universal Verification Methodology (UVM)
This 4 day course is for engineers interested in developing SystemVerilog verification environments using the latest Universal Verification Methodology (UVM).

Also available On Demand 

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Advanced Universal Verification Methodology (UVM)
This three-day workshop is designed for UVM users who want to take their skills to the next level.

Other HDL Courses

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Introduction to Verilog for RTL Design
A 3 day course teaching designers to write efficient, accurate RTL code for synthesis as well as basic testbenching and verification techniques.