Advanced Universal Verification Methodology (UVM)

This three-day workshop is designed for UVM users who want to take their skills to the next level.

Putting together real world testbenches require more than just knowing the components of the UVM library. Real world testbenches have issues that require knowing how to apply the UVM library to solve them. Issues such as multiple interfaces to the DUT, concurrent process synchronization, dealing with behaviors such as interrupts and multiple response types, and building scalable, reusable testbenches are addressed.

Based on years of UVM testbench development and consulting, this Advanced UVM class shares our experience in dealing with a host of testbench challenges. The class works through various issues and discusses common solutions with pros and cons of each. You will be able to apply these solutions to your testbench. You will also take away from this class several detailed real world example testbenches that provide a great reference for the future.

Topics

• Introduction
• DUT-TB Interface
• Encapsulation
• Configuration
• Configuration Object Distribution
• Container Classes
• Callbacks
• Heartbeat(Watchdogs)
• Message Catching (Demoting)
• Process synchronization
• Advanced Phasing
• Virtual sequences
• Response handling
• Interrupt handling
• Reset
• Error Injection
• Interface Classes
• UVM Register Model integration
• UVM Register Memory Allocation Manager
• Extension Objects
• Quirky Registers
• Command Line processing
• Coverage driven testing  

Hands-On Labs

A good portion of class time will be spent applying principles learned in lecture to hands-on labs.

Prerequisites

This is an advanced class and students are expected to have significant UVM experience or to have taken our UVM Introductory course plus experience on a couple of UVM projects.