Introduction to the Open Verification Methodology (OVM)

This 4 day course is for engineers interested in developing SystemVerilog verification environments using the latest Open Verification Methodology (OVM).

Students will first learn:

After mastering the basics, students will learn best-practice techniques to maximize the reusability of their test environments. Topics include:


Hands-On Labs

A good portion of class time will be spent applying principles learned in lecture to hands-on labs


WHDL SystemVerilog for Verification course or equivalent experience using SystemVerilog