Introduction to Verilog for RTL Design
A 3 day course teaching designers to write efficient, accurate RTL code for synthesis as well as basic testbenching and verification techniques.
This 3 day course is intended for designers who are new to Verilog and who wish to become familiar with the language with a particular emphasis on writing RTL code for synthesis. We also cover how to construct testbenches for unit level verification of your RTL code.
This course continuously mixes lecture and exercise. There is a simulation exercise for most topics providing a
very hands-on experience. Synthesizable constructs are clearly identified and appropriate synthesis coding
We can offer this class with most popular simulators.
- Verilog modeling
- Using your Simulator
- Verilog basics
- Procedural assignments
- Design a sequential pipe
- Synthesizing your design
- Programming statements
- Sensitivity lists
- Continuous assignments
- Timing accuracy
- Verification using Verilog
- Synthesis issues
- Finite State machines (exercise)
A digital design background and preferably some programming experience in C or another language.