Introduction to VHDL for RTL Design

A 4 day course teaching designers to write efficient, accurate RTL code for synthesis as well as basic testbenching and verification techniques.

This course is intended for designers who are new to VHDL. It focuses on teaching good RTL coding style for synthesis but also discusses basic testbenching and verification techniques.

This course continuously mixes lecture and exercise. There is a simulation exercise for most topics providing a very hands-on experience.


Syllabus

• VHDL Modeling

• Simulation Environment
  • VHDL Grammar
  • VHDL Objects
  • Data Types & Operators
  • VHDL Design Units
  • The Standard Logic Package

• Concurrent VHDL
  • Synthesis Issues

• Sequential VHDL
  • Simulation Cycle
  • Delta Delay
  • Sequential Statements
  • Synthesis Issues
    

• Structural VHDL
  • Synthesis Issues

• Writing Testbenches
  • Subprograms
  • File I/O

• Bidirectional Signals
• Finite State Machines

Prerequisites

A digital design background and preferably some programming experience in C or another language.