OVM to UVM Transition

This 2 day course is for engineers who are familiar with the Open Verification Methodology (OVM) and would like to learn testbench development with the Universal Verification Methodology (UVM). Covered are the new and updated features of UVM from OVM.

Topics

• Introduction to UVM
• Command Line Processor
• Phasing
• End of Test
• Configuration and Resources
• UVM registers

Hands-On Labs

A good portion of class time will be spent applying principles learned in lecture to hands-on labs

Prerequisites

WHDL OVM course or equivalent experience