SystemVerilog for Design

This course is 2 days long with an optional one day Verilog for Design precursor for 3 days total.

The course is aimed at RTL designers who wish to learn about the new features of SystemVerilog for RTL design.

The student will learn about the new constructs and features in SystemVerilog that are designed to capture design intent so that Simulation tools may analyze for correct RTL design practices and speed up the design process. Synthesis tools are not required.

Targeted labs are designed to reinforce the course material.

Syllabus

Hands-On Labs

A good portion of class time will be spent applying principles learned in lecture to hands-on labs

Prerequisites

RTL Design experience