Introduction to SystemC for Verification

This three-day workshop introduces the student to the SystemC C++ class library and to the SystemC Verification library.

This three-day workshop introduces the student to the SystemC C++ class library and to the SystemC Verification library. It is intended for engineers who are new to SystemC or those who may be self-taught, with an interest in learning SystemC for verification purposes. The student will learn how to write, compile, execute and debug system and hardware descriptions and testbenches with SystemC. This course is mixed lecture and exercises, with an exercise for nearly every topic.

Syllabus

• Introduction
  
• SystemC modeling
  
• Basic modeling structure
  
• Getting started - running & debugging
  
• Modules
  
  • Channels, ports, interfaces
    
  • Module constructor
    
  • Events
    
  • Processes in general
    
  • Thread processes
    
  • Method processes
    
  • Module instantiation (in modules)
    
• sc_main
  
• SystemC data types
  
• Primitive channels
  
• SystemC Verification
  
  • Data Introspection
    
  • Randomization
    
  • Constraints
    
  • Callbacks
    
  • Sparse arrays
    
  • Customizing Data Generation
    

Hands-On Labs

A good portion of class time will be spent applying principles learned in lecture to hands-on labs.

Prerequisites

• Introduction to C++ (2 days) training course
  • Course may be taken immediately before this course