Object Oriented Programming with SystemVerilog

This 2 day course is aimed at experienced Verification engineers who wish to learn more about Object Oriented Programming in SystemVerilog.

Object oriented programming is at the heart of any modern SystemVerilog verification methodology. And yet, it is often misunderstood. Too many projects suffer because engineers fail to implement the right class structure from the beginning making it hard to handle inevitable changes later on. This course starts with a review of the many ways classes are defined and used in SystemVerilog but then introduces and discusses a dozen popular Design Patterns that can take your testbenches to the next level. Particular emphasis is given to the often confused Inheritance and Composition patterns. UML diagrams and key design principles are introduced and used to illustrate all patterns.

Although most examples are pure SystemVerilog a number of the Design Patterns are also presented as deployed within the Universal Verification Methodology library. Everything you learn will be applicable within UVM and in custom SystemVerilog testbenches.

This course is taught for all the leading simulators.

Syllabus

• Object Oriented Programming with SystemVerilog
  
• Classes
  
  • Types
    
  • Constructors
    
  • typedef class
    
  • this and super
    
  • Virtual Methods
    
  • Hiding, parameterization and static
    
  • Virtual Classess
    
  • Up and Down casting
    
  • Interface Classes
    
• Design Patterns
  
  • Encapsulation
    
  • Template Method
    
  • Singleton and Lazy
    
  • Inheritance
    
  • Composite and Introspection
    
  • Interface
    
  • Strategy
    
  • Decorator
    
  • Observer
    
  • Callback
    
  • Object Pool and String Pool
    
  • Factory
    
• OOP Design Principles and Coding Styles
  
  • Single Responsibility
    
  • Substitution
    
  • Open Closed
    
  • Demeter
    
  • Encapsulation
    
  • Dependency Inversion
    
  • Style Topics: API, Naming, Readability, Magic Numbers, Timing
    

Hands-On Labs

A portion of class time will be spent applying principles learned in lecture to hands-on labs

Prerequisites

WHDL SystemVerilog for Verification training course or equivalent experience