SystemVerilog for Design

This course is 3 days long and starts with a day of Verilog for Design.

The course is aimed at RTL designers who wish to learn about the new features of SystemVerilog for RTL design.

The student will learn about the new constructs and features in SystemVerilog that are designed to capture design intent so that Simulation tools may analyze for correct RTL design practices and speed up the design process. Synthesis tools are not required.

Targeted labs are designed to reinforce the course material.

Syllabus

• Data types
  
  • User defined types
    
  • Enumeration
    
  • Casting
    
  • Parameterized types
    
• Tasks & Functions
  
  • SV Features
    
• Arrays & Structures
  
  • Packed Arrays
    
  • Unpacked Arrays
    
  • Structures
    
  • Unions
    
• Reducing RTL Ambiguity
  
  • Always Derivatives
    
• RTL Programming
  
  • Operators
    
  • Loops
    
  • Decisions
    
  • case/if..else
    
• Hierarchy
  
  • Ports
    
  • Implicit Port connections
    
  • Packages
    
• More Synthesis constructs
  
• Interfaces
  
  • Signal Style
    
  • Interface as a port type
    
  • Modports
    
  • BFM Style
    
• SVA
  
  • Immediate assertions
    
  • Concurrent assertions basics
    
  • Boolean expressions
    
  • Sequences
    
  • Property block
    
  • Verification directives
    
  • Sequence blocks
    
  • Sequence operators, methods & expressions
    
  • Property operators & expressions
    
  • Local Data values
    
  • Verification directives
    
  • Clocks
• Optional First day of Verilog RTL Precursor Content
  
  • Structure
    
  • Data types
    
  • Modules
    
  • Hierarchy
    
  • Procedural block
    
  • Procedural Assignments
    
  • if..else & case
    
  • Continuous Assignmentss
    
  • Taskss & Functions
    
  • Finite State Machines
    

Hands-On Labs

A good portion of class time will be spent applying principles learned in lecture to hands-on labs

Prerequisites

RTL Design experience